Transcript
Packaging
Presented By Siddhartha Sen, IIT Kharagpur Under the Guidance of : Prof. A. Dasgupta
Topics
Functions of the Package
Different Kinds of Packages
Rent’s Rule
VLSI Assembly Technology
System on Chip versus System in Package
3 – D Pa Pack ckag agiing
Chip on Chip (CoC)
Electrical Performance
Thermal Management
Common Failure Mechanisms and Reliability
Future Trends
Packaging
Topics
Functions of the Package
Different Kinds of Packages
Rent’s Rule
VLSI Assembly Technology
System on Chip versus System in Package
3 – D Pa Pack ckag agiing
Chip on Chip (CoC)
Electrical Performance
Thermal Management
Common Failure Mechanisms and Reliability
Future Trends
Packaging
Func Functi tion ons s of of the the Pack Packag age e-I
Packages shut out damaging external influences like Moisture, Dust, Vibration, Shock, Lightning, Magnets, etc and serve to protect silicon chips.
Lead frame allows electrical signals to be sent and received to and from semiconductor devices. Pack Packag agin ing g-1
Functions of the Package -II
Packages effectively release the heat generated by the chip during its operation.
Packages allow for enlargement of terminals size that makes the chips much easier to handle.
Pack Packag agin ing g-2
Types of Packages
Though a wide variety of packages can be used for VLSI devices, they can be broadly divided into two basic types:
Hermetic Ceramic Packages: The chip resides in an environment decoupled from the external environment by a vacuum tight enclosure. The packages are usually designed for high performance applications that allow some cost penalties
Plastic Packages: The chip is not completely decoupled from the external environment because it is encapsulated with resin materials, typically epoxy based resins. They are extremely cost competitive and their popularity persists because of rapid advances in plastic technology Pack Packag agin ing g-3
Types of Packages (Hermetic Packages)
The chip resides in a cavity of the package.
Chip
Package base material is ceramic usually Al203 or AlN.
The chip and the package are connected by fine Al wire.
Hermetic sealing is completed by a cap, usually ceramic or metal, lidded to the package.
Seal Ring
Leads Traces
A Typical Hermetic Package Packaging - 4
Types of Packages (Plastic Packages)
The chip is attached to the package of the lead frame.
The frame is made of etched or stamped thin metal( usually Fe-Ni or Cu alloys).
Interconnections are made by fine gold wire.
Encapsulation is carried out by Transfer-molding using epoxy resin. Packaging - 5
Molding Material
Chip Support Paddle Spot Plate
Bond Wires
Types of Packages (PWB level)
Packaging - 6
Rent’s Rule Prediction
Rent’s Rule is an empirical relationship between the gate count and the I/O (Terminal) Count in a Chip.
Microprocessors
Logic Array
Number (I/O Count ) = α (Number of gates)
Typically:
α = 4.5 β = 0.5
β
DRAM Memory : 1 Kbits – 1024 Kbits Microprocessors : 4 – 32 bits Gate Arrays : 50 – 16K gates Packaging - 7
VLSI Assembly Technologies Wafer Solder Preform Polymer Adhesive Al wire / Au wire Conformal Coating Metal Preform Polymer Seal Molding Compound
Wafer Preparation
Wafer Backgrinding Die Preparation
Die Bonding
Adhesive Die Bonding
Die Interconnection
Wire Bonding, TAB,
Molding
Transfer molding
Eutectic Die Bonding
Flip Chip
Package Seal Marking DTFS
Ink Marking Laser Marking Deflash-Trim-FormSingulate
Wafer Backgrinding
Wafer Backgrind is the process of grinding the backside of the wafer to the correct wafer thickness prior to assembly.
Wafers normally undergo a cleaning and surface lamination process prior to the actual backgrinding process.
The grinding wheel parameters are: speed, spindle coolant water temperature and flow rate, initial and final wafer thickness, and feed speeds.
Continuous washing of the wafer is also done during the backgrinding process to remove debris. Packaging - 9
Die Preparation
Wafer Mounting: frame loading, wafer loading, application of tape to the wafer and wafer frame, cutting of the excess tape and unloading of the mounted wafer
Wafer mounted on wafer frames
Wafer Films
Wafer Saw: alignment, cutting by resin-bonded diamond wheel, cleaning Packaging - 10
Wafer Saw Blades
Die Bonding
Die Bonding is the process of attaching the silicon chip to the die pad or die cavity of the support structure.
Adhesive
Die Attach: Uses adhesives such as polyimide, epoxy and silver-filled glass as die attach material
Eutectic Die Attach: Uses a eutectic alloy to attach the die to the cavity. The Au-Si eutectic alloy is the most commonly used Packaging - 11
D/A adhesive as the grainy material between the die and die pad
Normal Eutectic Die Attach and with Balling
Die Interconnection: Wire Bonding
The wire is generally made up of one of the following:
Gold
Aluminum
Copper
There are two main classes of wire bonding:
Ball bonding
Wedge bonding
Wire Bonds
Packaging - 12
Wire Bonding (Ball-Bonding) A
gold ball is first formed by melting the end of the wire.
The free-air ball brought into contact with the bond pad, adequate amounts of pressure, heat, and ultrasonic forces are then applied. The wire is then run to the corresponding finger of the leadframe, forming a gradual arc or "loop" between the bond pad and the leadfinger. Packaging - 13
The 1st Bond
The 2nd Bond
Gold wire ball-bonded to a gold contact pad
Wire Bonding (Wedge Bonding) A
clamped wire is brought in contact with the bond pad. Ultrasonic energy and pressure are applied.
The wire is then run to the corresponding lead finger, and again pressed. The second bond is again formed by applying ultrasonic energy to the wire. Packaging - 14
1st Wedge Bond
Aluminum wires wedge-bonded
Die Interconnection: Flip Chip
The term “Flip-chip” refers to an electronic component or semiconductor device that can be mounted directly onto a substrate, board, or carrier in a ‘face-down’ manner.
Electrical connection is achieved through conductive bumps built on the surface of the chips, which is why the mounting process is ‘facedown’ in nature. Packaging - 15
Flip Chip Bumps
Flip Chip - Advantages
Smallest Size
reduces the required board area by up to 95%
requires far less height
Highest Performance
reduces the delaying inductance and capacitance of the connection by a factor of 10
highest speed electrical performance of any assembly method
Most Rugged
Lowest Cost Packaging - 16
Tape Automated Bonding (TAB) A
process that places bare chips onto a printed circuit board (PCB) by attaching them to a polyimide film. The film is moved to the target location, and the leads are cut and soldered to the board. The bare chip is then encapsulated ("glob topped") with epoxy or plastic. Packaging - 17
Molding
Molding is the process of encapsulating the device in plastic material.
Transfer molding is one of the most widely used molding processes in the semiconductor industry.
The cavities are filled up in a 'Christmas tree' fashion - The highest filling velocity is experienced by the first cavity.
Subsequent cavities are filled with increasing velocities until the last cavity, which ends up with the second highest filling velocity.
Wiresweeping and die paddle
Packaging - 18
Mold Chases
Examples of Molds
Package Sealing
Sealing is the process of encapsulating a hermetic package, usually by capping or putting a lid over the base or body of the package. The method of sealing is generally dependent on the type of package.
Ceramic DIPs, or cerdips, are sealed by topping the base of the package with a cap using seal glass.
Seal glass, like any glass, is a supercooled liquid which exhibits tremendous viscosity when cooled below its glass transition temperature. A seal glass may be classified as vitreous or Devitrifying. Packaging - 19
Marking
Marking is the process of putting identification, traceability, and distinguishing marks on the package of an IC.
The most common Ink marking process for semiconductor products is Pad printing. Pad printing consists of transferring an ink pattern from the plate, which is a flat block with pattern depressions that are filled with ink, to the package, using a silicone rubber stamp pad.
Laser marking refers to the process of engraving marks on the marking surface using a laser beam. There are many types of lasers, but the ones used or in use in the semiconductor industry include the CO2 laser, the YAG laser, and diode lasers. Packaging - 20
Deflash/Trim/Form/Singulation (DTFS) 1. Deflash - removal of flashes from the package of the newly molded parts. Flashes are the excess plastic material sticking out of the package edges right after molding. 2. Trim - cutting of the dambars that short the leads together. 3. Form - forming of the leads into the correct shape and position. 4. Singulation - cutting of the tie bars that attach the individual units to the leadframe, resulting in the individual separation of each unit from the leadframe. Packaging - 21
System on Chip ( SoC ) versus System in Package (SiP)
SoC is a technology that allows a system to be built on one silicon chip (bare chip).
SiP is a package technology that combines a multiple number of readymade chips (such as logic and memory) and encases them in one package as one system. Packaging - 22
SiP Categories
Packaging - 23
3D Packaging: Introduction
The driving forces are the significant size and weight reductions, higher performance, small delay, higher reliability and reduced power.
3 D Packages score over conventional packages in:
Size and Weight
Silicon Efficiency
Interconnect Usability and Accessibility
Delay
Noise
Power Consumption
Speed
Packaging - 24
Four-die stack including two spacers
3D Packaging Types of 3D Packages
Stacked Die Packages: Consists of bare die stacked and interconnected using wire bond and flip-chip connections in one standard CSP
Stacked-Packages: consist of stacked, pre-tested packages or a mix of KGD and packages. These are interconnected using wire bond, flip chip or solder balls on one CSP
They can be:
Package-in-Package (PiP)
Package-on-Package (PoP) Packaging - 25
PiP structure with 4 stacks
PoP structure with 4 stacks
3 D Packaging: Advantages - I
The shift from conventional single chip packages to 3D technology, leads to substantial size and weight reductions: Volume ( in cm3 / Gbit ) Type
Capacity
Discrete
Planar
3D
Discrete/3D
Planar/3D
SRAM
1 Mbit
1678
783
133
12.6
5.9
DRAM
1 Mbit
1357
441
88
15.4
5.0
Mass ( in grams / Gbit ) Type
Capacity
Discrete
Planar
3D
Discrete/3D
Planar/3D
SRAM
1 Mbit
3538
2540
195
18.1
13.0
DRAM
1 Mbit
2313
1542
132
17.5
11.6
Packaging - 26
3 D Packaging: Advantages - II
Increase in Silicon Efficiency. Interconnect Usability and Accessibility.
Packaging - 27
3 D Packaging: Advantages - III
Delay Reduction
Noise Reduction
Power Reduction
Speed Increase
Packaging - 28
3 D Packaging: Limitations
There are trade-offs which need to be taken into account when using 3D technology in system design:
Thermal Management
Design complexity
Cost
Time to Delivery
Design Software
Packaging - 29
Electrical Considerations: Introduction
The choice of a package for an integrated circuit depends on the electrical and thermal conditions under which the chip is expected to operate. In other words, the package must satisfy a set of electrical and thermal requirements formulated for the application at hand.
The electrical operating conditions of an integrated circuit can be viewed as consisting of two distinct environments: one for Signals and another for Power . The requirements for these environments are substantially different. Packaging - 30
Electrical Considerations: The Signal Environment
The signal's electrical environment is the arrangement of conductors and dielectrics. Electrically, each segment of this path represents a transmission line with certain characteristic impedance and time delay. Also involved are the inductances of the bond wires and package pins.
Usually, the leads are not of controlled impedance and each possesses substantial inductance and capacitance. Relatively strong inductive and capacitive coupling (M and C) exist between the leads.
The major issues in the signal environment are Signal Delay, Signal Reflection and Noise Reduction. Packaging - 31
Electrical Considerations: The Signal Environment
Signal Delay
High speed operation requires lower interconnect delays. The maximum achievable operating frequency is obviously the inverse of the critical delay path.
In package construction, a short signal line (bonding wire length plus lead length) in small dielectric material, typically polyimide resin, is preferable.
An
excessively small dielectric constant of the surrounding material, however induces signal reflections that degrade operating speed.
Packaging - 32
Electrical Considerations: The Signal Environment
Signal Reflection:
Mismatched impedances cause signal reflections when a signal is l transmitted via a transmission line. The transmission line character cannot be ignored when the signal lines are long
c <
v0
ε
Multilayered packages like stripline structures and microstrip structures provide better impedance matching Packaging - 33
r
Stripline conductor
Microstrip conductor
Electrical Considerations: The Signal Environment
Noise: The two kinds of noise of importance are Cross-Talk noise and Simultaneous switching noise:
Cross Talk Noise: Line is undesirably affected by another line due to electromagnetic coupling
Simultaneous Switching Noise: Occurs when many output buffers switch simultaneously Packaging - 34
Cross Talk on Adjacent Lines
Tx Line Simultaneous Switching Noise
Electrical Considerations: The Power Environment
Inductances in the power circuit cause instability of the potentials at the power and ground terminals of the chip:
Power Supply Droop
Ground Bounce
Packaging - 35
Electrical Considerations
The Desirable Electrical Characteristics: Low ground resistance (minimum power supply voltage drop) Minimum Self Inductance of signal leads (short signal leads) Minimum power supply spiking due to simultaneous switching of signal lines. Minimum Mutual Inductance and Cross Talk (short paralleled signal runs) Minimum Capacitive loading (short signal runs near a ground plane) Maximum use of Matched Impedances (avoid signal reflection)
Packaging - 36
Thermal Management
Efficient and cost-effective removal of dissipated thermal energy from the device to assure its reliable performance over the long term.
Effects of Increasing Temperatures:
Device physics is strongly influenced by the junction temperature
Corrosion and interfacial diffusion mechanisms
Approximately
a 10°C increase in temperature reduces the mean time to failure by a factor of two
Packaging - 37
Thermal Management (Thermal Resistance)
The internal temperature (called junction temperature) is equal to the ambient temperature plus an offset proportional to the internal power dissipation P. It is given by: T junction = Tambient + θJA.P
The constant of proportionality
Current Trends:
θJA
is called the thermal resistance
The total power is going up due to improper scaling, higher packing density, and lower chip size
Maximum ambient being as high as 60 °C
Maximum junction temperatures from 105 °C to 65 °C
The total thermal resistance of the package must decrease: θJA = θJC + θCA
Packaging - 38
Thermal Management
A Simplified Heat transfer model: Heat is transferred from the chip to the surface of the package by conduction and from the package to the ambient by convection and radiation:
Ta
Thermal Convection & Radiation
Tc Conduction T j
θJA = θJC + θCA
= ((T j-Tc) + (Tc-Ta))/P Chip θJC is mainly a function of package
materials and geometry θCA depends
PWB
Simplified Heat Transfer Model of a packaged chip
on package geometry, the package orientation and conditions of ambient. Packaging - 39
Thermal Considerations
Conduction dominates heat transfer from chip to package surface. One Dimensional Fourier’s equation gives: Q = (T1 – T2)*κ*(S/L) In the actual package: P = (T j – Tc)*κ*(S/L) Thus we have: θJC =
(T j – Tc)/P = L/(κ*S)
VLSI packages have a high packing density (small S) so high thermal conductivity components such as Cu alloys lead frames, AlN substrates and thermo-conductive molding compounds are particularly important as they increase overall package κ value.
Thinner packages (low L) are also important. Packaging - 40
Thermal Considerations
Convection: Heat transfer from the package surface to the ambient results mostly from convection, given by Newton’s Cooling Law: Q = h*A*(Tc – Ta) Therefore: θCA =
(Tc – Ta)/P = 1/(h*A)
θCA is
reduced through increased conduction and larger package surface area. The application system constructions are forced air convections, liquid coolants in place of air coolings and additional heat sinks attached to the package surface.
Packaging - 41
Thermal Considerations
Radiation helps transfer some heat from the package surface to the ambient, but usually the contribution is small. According to Stefan-Boltzmann Law: Eb = ε*σ*T4 The heat radiated is:
Q = σ*f*A*(T14 – T24)
Where f is given by:
f = 1/((1/ε1)+(1/ε2)-1)
When T1-T2<