Development Of Jtag Verification Ip In Uvm Methodology

Transcript

IEEE 1149.1/1149.6 (JTAG) Verification IP provides a smart way to verify the IEEE 1149.1/1149.6 (JTAG) component of a SOC or an ASIC. The SmartDV's JTAG Verification IP works in a highly randomized manner to generate wide range of scenarios for effective verification of DUT(device under test).JTAG VIP includes an extensive test suite covering most of the possible scenarios and detection of protocol violation using an effective protocol-checker. IEEE 1149.1/1149.6 (JTAG) VIP is supported natively in System Verilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification environment.