Transcript
CHINA JILIANG UNIVERSITY NAME: MAHAMED AHMED ID: 20121101 COURSE TITLE: DIGITAL SYSTEM DESIGN PROJECT: DIGITAL CLOCK
INTRODUCTION: A digital clock is a type of clock that displays the time digitally (i.e. in numerals or other symbols), as opposed to an analog clock, where the time is indicated by the positions of rotating hands. Digital clocks are often associated with electronic drives, but the "digital" description refers only to the display, not to the drive mechanism. (Both analog and digital clocks can be driven either mechanically or electronically, but "clockwork" mechanisms with digital displays are rare.
Purpose: The main purpose of this project was to understand how to design and the implementation of digital clock using Verilog HDL.
SPECIFIC PURPOSE: The following were specific purpose. The designed program must count hours from 00:00:00 to 23:59:59 using eight seven segment The digital clock design using Magic SOPC experiment box. That means the pins assignment must be finished.
OBJECTIVES the aim of this practical course is to perform a system design and test the designed circuits are to be implemented on an Altera DE2115 board I have learned from this course how to design and synthesize of sequential circuit using Verilog code Fitting a synthesized circuit into an Altera FPGA Simulating the design circuit Programming and configuring the FPGA chip on Altera’s DE2-115 board
CONSTRUCTION
Digital clocks typically use the 50 or 60 hertz oscillation of AC power or a 32,768 hertz crystal oscillator as in a quartz clock to keep time. Most digital clocks display the hour of the day in 24-hour format; in the United States and a few other countries, a more commonly used hour sequence option is 12-hour format[citation needed](with some indication
of AM or PM). Emulations of analog-style faces often use an LCD screen, and these are also sometimes described as "digital" To represent the time, most digital clocks use a seven-segment LED, VFD, or LCD display for each of four digits. They generally also include other elements to indicate whether the time is AM or PM, whether or not an alarm is set, and so on..
Verilog HDL codes Below are Verilog codes designed for the implementation of the digital clock.
The code of the counter 24
module count24(qout,cout,data,load,cin,reset,clk); output[7:0]qout; output cout; input[7:0]data; input load,cin,clk,reset; reg[7:0]qout; always@(posedge clk) begin if(reset) qout<=0; else if(load) qout<=data; else if(cin) begin if((qout[3:0]==3)&&(qout[7:4]==2)) begin qout[3:0]<=0; qout[7:4]<=0; end else if (qout[3:0]==9) begin qout[3:0]<=0; qout[7:4]<=qout[7:4]+1; end else qout[3:0]<=qout[3:0]+1; end end assign cout=((qout==8'h23)&cin)?1:0; endmod
the code of the counter 60
module count60(qout,cout,data,load,cin,reset,clk); output[7:0]qout; output cout; input[7:0]data; input load,cin,clk,reset; reg[7:0]qout;
always@(posedge clk) begin if(reset) qout<=0; else if(load) qout<=data; else if(cin) begin if(qout[3:0]==9) begin qout[3:0]<=0; if(qout[7:4]==5) qout[7:4]<=0; else qout[7:4]<=qout[7:4]+1; end else qout[3:0]<=qout[3:0]+1; end end assign cout=((qout==8'h59)&cin)?1:0; endmodule
the code of the freq-divider module fredivider(clk,rst,clk_out,count); input clk,rst; output reg clk_out; output reg [25:0] count; parameter n=50000000; always@(posedge clk or negedge rst) begin if(~rst) begin count<=4'b0; clk_out<=1'b0; end else if(count
