Transcript
In any processor the major units are Control Unit, ALU and Memory read write. Among these units the performance of any processor majorly depends on the time taken by the ALU to perform the specified operation. Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate (MAC) and inner product are among some of the frequently used Computation Intensive Arithmetic Functions (CIAF) currently implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform (FFT), filtering etc. Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. Vedic Mathematics is the name given to the ancient system of mathematics, or to be precise, a unique technique of calculations based on simple rules and principles with which any mathematical problem can be solved – be it arithmetic, algebra, geometry or trigonometry. The system is based on 16 Vedic sutras or aphorisms, which are actually word formulae describing natural ways of solving a whole range of mathematical problems. The task in this progress report is to show the novel multiplier design developed in the Tanner tool software of Very Large Scale Integration (VLSI). Performance of this multiplier is much faster and consumes less power than the recently developed multiplier architectures.
